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01/27/2011

Why would anyone bolt-down mount an RF device?

January 28, 2011
(originally appeared in EETimes, May 15, 2009)


Leonard Pelletier-2


Leonard Pelletier is the Application Support Manager for Freescale RF in Tempe, AZ and is in charge of providing technical assistance to the amplifier design community. He has been with the company since 1995 working in this position supporting any and all RF applications. Prior to his work with RF components, Mr. Pelletier held amplifier design engineering positions with both the Motorola Cellular Infrastructure Group in Arlington Heights, IL and the Motorola RF Products Division in Torrance, CA. This blog is part of Microwave Journal's guest blog series.


To comment or ask Leonard a question, use the comment link at the bottom of the entry.


 

As a member of an application-support team, we regularly write and rewrite several application notes dealing with how to mount the RF transistors for maximum RF performance.

Through history, application notes such as AN1040, AN1041, AN1617, AN1673, AN1674, AN1907, AN1918, AN1923, and the latest versions of AN1949, AN3263 and AN3789, all deal with recommendations for device mounting.

The one item that is missing from all of these application notes is the total benefit of solder-mounting the devices when compared to any form of screw or clamp mounting. Some of these application notes compare various forms of thermal interface materials on RF performance, but they all stay within the confines of the particular mounting method.

What is missing is an application note that jumps across all three popular mounting methods and only compares the RF performance capability of the devices across mounting variations. If that were to occur, the clear winner would be the pure solder-mount method as mentioned in application note AN1907.

In the standard Freescale manufacturing test process, we typically clamp the device to a bare-copper heatsink under approximately 250 pound/in2 (PSI) average pressure, with either thermal grease or no thermal-interface material whatsoever. Under those test conditions, we get the standard RF-performance parameters that one sees in the data sheets and as reported on our manufacturing test data reporting system.

All well and good, but some of our more experienced customers know that those reported numbers are not the true capability of the devices. When one solder mounts the parts rather then clamping or bolting, the whole set of RF performance numbers goes up significantly. Performance increases on the order of 1 dB in gain, 1% in efficiency, and perhaps as much as 2 dBc in ACPR are quite common, along with a reduction in maximum die operating temperatures, by as high as 20°C.

This cooler die temperature is one of the key drivers that lead to the increased RF performance, along with the improved, lower-resistance common source impedance through the back-side solder-mounting of the device. In addition, for silicon-based devices, every 10 to 15°C reduction in junction temperature results in doubling of mean time to failure (MTTF), leading to a more reliable power amplifier.

So why would anyone bolt-down mount an RF device? Only because they did not know the significant benefits involved with solder mounting. And now you do.


 

01/06/2011

The Most Common High Power RF Design Error

December 15, 2010


Leonard Pelletier-2


Leonard Pelletier is the Application Support Manager for Freescale RF in Tempe, AZ and is in charge of providing technical assistance to the amplifier design community. He has been with the company since 1995 working in this position supporting any and all RF applications. Prior to his work with RF components, Mr. Pelletier held amplifier design engineering positions with both the Motorola Cellular Infrastructure Group in Arlington Heights, IL and the Motorola RF Products Division in Torrance, CA

To comment or ask Leonard a question, use the comment link at the bottom of the entry.


 

The Most Common High Power RF Design Error: Inadequate Back-Side Grounding of the Source Contact Connection

 

Here in the Freescale Application Support Department, we get lots of calls from RF design engineers, who are in a desperate, crises mode.  They have created a design using the best simulation tools possible and after having just built up their first prototype units, they are having some sort RF performance issues of varying degrees.  Sometimes it is poor RF performance numbers not in line with the data sheet, sometime it is spurious oscillations, or shifting RF performance numbers with temperature or maybe even, in extreme cases, total device failures.         

          By a wide margin, the number one cause for most of the above mention design problems can be traced back to a serious shortcoming in the back side RF grounding connection of the device and its’ contact with the associated PCB ground plane.

 

There are two key assembly requirements that must be accomplished by the devices’ back side interface.

The interface must provide a good thermal contact between the RF device and heatsink.  This interface needs to be flat, smooth, and maybe have a microscopic gap filing interface material like solder, thermal grease or a very thin elastomeric pad of some sort.  All of these attributes are needed in order to facilitate the heat flow out of the device and into the heatsink-to-air assembly.

 

Some common mistakes made here include excessive solder voiding, excessive thermal grease thickness and excessively rough machined surfaces with no gap filling material.

 

 The second item that must be created in the back side interface is a solid, consistent RF plainer ground.  Not a DC point ground but a broad, ultra low electrical resistance connection between the back side of the RF device and the back side of the PCB.  Notice I did not say heatsink.  The heatsink may be used as part of the grounding structure or it may not, but the key required function is to mesh the PCB ground plain and the RF device’s ground plain with a low resistance, high currant carrying assembly method. 

 

 

Most common mistakes that occur in this regard are associated with the PCB grounding.  At low frequencies and low RF powers, one can screw the PCB to the heatsink and create point contact DC grounds.  That just does not work at the higher frequency above 500 MHz and higher powers above 100W.  One needs to solder the back side ground of the PCB to the back side ground of the RF device thru a copper carrier or heat spreader assembly in order to be able to handle the very high RF circulating currants that are created in this area.

 

At RF power levels above 100W and with low RF impedances at the device’s leads( near 1 ohm), the RF currents tend to be very large.

P= I**2/R or I=10 Amps in the given example.  Designers take great pains to make sure the top side PCB impedance matching structure is consistent, robust, repeatable and has a ultra low RF resistance connection. But if there is 10 amps of RF current flowing on the top side of the PCB, then there is also 10 amps flowing on the back side ground plain between the PCB and the RF device and yet that interface structure is often largely uncontrolled. The back side ground consistency is just as important as the top side matching consistency and yet the back side ground is never documented, rarely measured and very often overlooked.

 

 Another common mistake is to apply a chemical chromate finish to the aluminum heatsink to prevent oxidation.  Class 3 is the insulating version and Class A1 is consider electrically conducting but the reality is that both prevent the ultra low contact resistance that is required in a back side RF grounding application.  That is why the heatsink is a poor choice in providing the electrical connection between the PCB and the RF part.  A much better design methodology is to have a consistent, robust, fully soldered assembly that controls both the top side matching and the back side return path thru a carrier, coin, heat spreader or PCB back side metal layer.

 

 Fig1_Ea_122010

 

 

 

Picture 1, Three methods of mounting a RF power Device.  From the left, True Surface Mount Soldered with Gull-Wing Leads, Back Side Solder Down, and Screws with a Center-Pushing Clamp.

Conclusions

Clearly a fully soldered assembly in the critical area between the back side source of the device and the PCB ground plane thru a heat spreader is the design optimum solution.  Anything less and one is asking for trouble.

 For reference, here is a list of mounting application notes that are available from the freescale.com/rfpower web site: AN1908, AN1940, AN2467, AN3778 and AN3789


 

Three little known facts about the high-power RF products market

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December 9, 2010

Freescale


Leonard Pelletier-2


Leonard Pelletier is the Application Support Manager for Freescale RF in Tempe, AZ and is in charge of providing technical assistance to the amplifier design community. He has been with the company since 1995 working in this position supporting any and all RF applications. Prior to his work with RF components, Mr. Pelletier held amplifier design engineering positions with both the Motorola Cellular Infrastructure Group in Arlington Heights, IL and the Motorola RF Products Division in Torrance, CA


Most people working in the high power RF design arena think that they know a fair amount about high power RF products and the devices that comprise that market space.   I am here to tell you that there are three relatively interesting and unknown facts about the high power RF product market that the consumers generally do not comprehend.

One common assumption is that the RF power market is all about the larger, above 100W, high power parts and those are the types of products that sell the best.
Simply not true. In RF power, there is a large demand for a lot of low power, sub 5W devices, for drivers, pre-drivers and for signal management and control. About 25 percent of Freescale Semiconductor’s RF power device sales are for sub 5W, semi-low power amplifier components.

People tend to think that the RF power market is all about the high cost, gold plated, air cavity, flange mount ceramic packaged parts.
False. Overmolded plastic packaged parts outsell ceramic devices at about a 4 to1 ratio. Currently, high power plastic is limited to about 300W CW but it is the approximately 20 percent lower price advantage of overmolded plastic that makes it so attractive, hence its larger market share.

People tend to believe that the RF power market is limited to a handful of devices in a limited range of power levels and package types.
Wrong again. Freescale contains over 235 different RF power devices in their portfolio, including 21 different 100W parts at various frequencies and at least 45 parts with a P1dB rating at or below 10 watts.

This high granularity of the power level selection allows for fine degrees of design output power selection.  In most RF amplifier designs, the selection of a device with an extra 10 percent larger power capabilities might make a lot of sense, from a design margin point of view.  But when that excessive output power capability increases the cost of the design by 2 percent and reduces the DC to RF conversion efficiency of the design by another 2 percent, then those trade-offs are usually deemed unacceptable.

So there you have it.  Three previously little know facts about the RF power market and now, presented here, the real inside scoop.  Enjoy.

 

 

RF Leonard - follow me at www.twitter.com/RFLeonard

 

07/09/2009

What defines LDMOS Ruggedness: Obsolete VSWR Tests gives way to “Fast Times at Doherty High”

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July 9, 2009

Freescale


Leonard Pelletier-2


Leonard Pelletier is the Application Support Manager for Freescale RF in Tempe, AZ and is in charge of providing technical assistance to the amplifier design community. He has been with the company since 1995 working in this position supporting any and all RF applications. Prior to his work with RF components, Mr. Pelletier held amplifier design engineering positions with both the Motorola Cellular Infrastructure Group in Arlington Heights, IL and the Motorola RF Products Division in Torrance, CA

To comment or ask Leonard a question, use the comment link at the bottom of the entry.


In the RF LDMOS semiconductor business, everything is constantly changing.  The applications change, the device requirements change, the customer’s expectations change and of course, the competition changes.

 

The latest applications change in the LDMOS market space is one of improved ruggedness and how to properly define and test the device’s new ruggedness criteria.  In the ancient chronicles of past LDMOS history, we always talked about the standard universal test of applying a constant input CW test signal, of a high power level and maybe even an elevated VDD, then operating the device into a relatively nasty, high VSWR load test condition at all load phase angles to see if we could cause an electrical overstress event and damage the parts.

 

The all phase angle requirement was there to insure that the parts experienced both the high current stress of a low impedance load and the high voltage swings of a high impedance VSWR event.  High current would stress the thermal design and high voltage would stress the voltage breakdown limits.

 

The problem was that this VSWR test did not really match the ruggedness requirements of the field applications.  Yes, they simulated open circuit cables or ice covered antennas, but with modern LDMOS devices, the typical worst case range of these tests were of such a low stress level that they did not produce any failures in the course of normal operation.

 

With the new Doherty applications, we were starting to see occasional failures in the peaking amp device side, even though that device, in theory, had the lesser stress of the two sides, as defined by the standard VSWR criteria.  It turned out that those devices were failing not due to thermal or standard, steady state DC voltage breakdown issues, but due to dV/dT induced snapback failures due to the rapidly changing nature of the peaking signal.

 

Investigations into the fast rise time snapback ratings of the various generations of LDMOS showed that there was very poor correlation between VSWR ruggedness and snapback ruggedness ratings.

 

Fortunately, we were able to change some of the internal design optimizations of our latest LDMOS structures and significantly improve their snapback ratings, both in a peak voltage level and in a peak current-to-failure rating.

 

So we will end this blog with a new rule of thumb for dV/dT induced snapback ruggedness ratings:

 

All 50V and 900 MHz HV8 devices are good for pulse rise times as short as 10 nSec.  All other devices are limited to greater than 100 nSec.

 

This rule will change as more devices are rolled out in the future, but for the next 6 months, this will remain a valid assumption…

 

RF Leonard - follow me at www.twitter.com/RFLeonard

05/26/2009

Innovate or Die: Next Gen LDMOS Process Improvements

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May 26, 2009

Freescale


Leonard Pelletier-2


Leonard Pelletier is the Application Support Manager for Freescale RF in Tempe, AZ and is in charge of providing technical assistance to the amplifier design community. He has been with the company since 1995 working in this position supporting any and all RF applications. Prior to his work with RF components, Mr. Pelletier held amplifier design engineering positions with both the Motorola Cellular Infrastructure Group in Arlington Heights, IL and the Motorola RF Products Division in Torrance, CA

To comment or ask Leonard a question, use the comment link at the bottom of the entry.


In the semiconductor business, everyone is constantly revitalizing their portfolio, improving on the capability of their devices to make the next generation of parts significantly better than what is available now. Run faster, jump higher, PF flyers. The semiconductor business model is “innovate or die”. Either you are moving forward and winning or you are not-so-slowly dying. Competition drives the requirement for innovations and the fastest innovators typically have the best products, broadest portfolio base and the largest market share.

LDMOS is no stranger to this innovation requirement, and given that it takes, on average, about 18 months to create a new generation product platform, then it is high time we start seeing the 8th generation (HV8) series of devices start rolling out of the factory.

HV8 is different. You may have heard this before with previous generations and in this case, it is also true. The requirement for improved efficiency is always one of the main drivers for innovation, but the way HV8 achieves this goal is different from past generations of devices. Most of the HV8 improvements came about by reconfiguring the active channel, drain extension region of the LDMOS structure. Here, by altering the doping levels and controlling the electric field intensity, we can optimize the impact ionization potential.  In this case, lower is better and lower impact ionization levels translate to a device with significantly improved ruggedness and lower hot carrier injection, which in turn reduces Vgs drift.

Ldmosmay22

This channel optimization, along with some alternative top metal changes produces a generation of devices that have a 20% higher power density, on a watts per mm basis.  A 20% improvement in power density translates to higher terminal impedances, wider bandwidth capability and 5 points higher efficiency at the P1dB compression level.

In addition to power and efficiency improvements, HV8 devices also have improved raw and DPD correctable linearity, which is the result of a 30% - 50%  reduction in AM/PM phase distortion levels compared to HV7 devices.  The efficiency and linearity improvements combine to create a device with significantly better performance in both traditional Class AB and Doherty amplifier configurations.

So it is innovate or die, and the improvements of HV8 show that LDMOS is not planning on pushing up daises anytime soon.

RF Leonard – follow me at www.twitter.com/RFLeonard
#IMS2009 - Coming up next:  A New Test for Ruggedness: Fast Rising dV/dT

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